Conventionally, technology shortens the time consumed for circuit simulation and generates test scenarios based on state transition tables.
Nonetheless, with the conventional technologies above, for a finite state machine (FSM) model of a circuit-under-test, states that should be saved, restored, etc. cannot be identified and thus, design engineers must manually designate the states, resulting in a large burden on the engineers. Further, since such designation is dependent on the ability of the design engineer, differences in designation arise among the engineers and in some cases, the simulation time cannot be reduced adequately.
Typically, even for the same circuit-under-test, since the test scenarios and the FSM model are created by the design engineer, it takes time before the simulation is conducted and the burden on the design engineer becomes great.
Further, if discrepancies arise between the created test scenarios and the FSM model, simulation must be repeated, resulting in an increase in the simulation time. A problem further arises in that if paths that are substantially the same in the FSM model are stored as different paths, each of the paths must be simulated, increasing the simulation time.